1. Field of the Invention
The present invention relates to a photomask used in a thermal flow process, a method of forming patterns used in a thermal flow process, and a semiconductor integrated circuit in which a portion having fine planar shapes is treated by a prescribed process through openings in a resist.
2. Description of the Related Art
In recent years, fine-patterned semiconductor integrated circuits constructed by using thin-film techniques are being used for a variety of purposes, and these constructions are increasing in fineness with each year. As an example, photolithography is one technique for achieving fine patterning of the layers of a semiconductor integrated circuit.
In a case of forming through-holes in the insulating film of a semiconductor integrated circuit, a resist is applied to the surface of the insulating film that is to undergo processing, and the resist is then exposed using a photomask in which a plurality of exposure openings are formed. The resist is then developed to form openings at the exposed portions, and this resist is used as a mask to etch the insulating film through the openings.
This type of photolithography is used not only for the formation of through-holes described above but for various other purposes such as introducing impurities into a semiconductor substrate and patterning wiring lines. In this type of photolithography, a photomask is formed in which the pattern that is to be exposed is enlarged in all directions, following which the exposure process is carried out with this photomask using reducing optics to expose a pattern of the desired dimensions on the resist.
In this technique, a pattern that is finer than a prescribed dimension cannot be exposed due to the limits of optical resolution. However, there is now demand to reduce resist openings below the exposure limit dimensions, and the thermal flow process has been developed as a means of realizing such a reduction.
Referring now to FIG. 1A-FIG. 2C, one example of the thermal flow process of the prior art is next described.
As shown in FIG. 1A, a DRAM (Dynamic Random Access Memory) that is in the process of fabrication is first prepared as semiconductor integrated circuit 100, which is the object of processing. In semiconductor integrated circuit 100 that is here taken as an example, gate oxide film 102 is formed on the surface of semiconductor substrate 101, and gate electrodes 103 and 104 of the transistor elements that will serve as memory cells are formed in a prescribed pattern on the surface of this gate oxide film 102. Gate oxide film 102 is partitioned by element isolation regions 105 according to the positions of memory cells, and the space around gate electrodes 103 and 104 is filled with interlayer dielectric film 106, which is a prescribed layer.
In semiconductor integrated circuit 100 which is taken as an example here, contact hole 107 of a bit contact is formed from the surface of interlayer dielectric film 106 to the surface of gate oxide film 102 at a position between the pair of gate electrodes 103 and 104, as shown in FIG. 2C. Photomask 111, in which is formed exposure opening 110 that corresponds to this contact hole 107, is therefore prepared as shown in FIG. 1C.
The structure of this photomask 111 is such that shield film 113 is formed on the underside of transparent base member 112 and exposure opening 110 is formed by partially removing this shield film 113. This exposure opening 110 is formed at position that corresponds to contact hole 107, and its dimensions in all directions are greater than the dimensions of contact hole 107.
Resist 115 is then applied to the surface of interlayer dielectric film 106, which is a prescribed layer of semiconductor integrated circuit 100, to form a prescribed film thickness as shown in FIG. 1B, and the above-described photomask 111 is arranged parallel to and confronting the surface of resist 115 at a prescribed distance from the surface of resist 115.
In this configuration, resist 115 is exposed to light by exposure device (not shown in the figure) through exposure opening 110 of photomask 111, and as shown in FIG. 2A, this resist 115 is then developed to form opening 116 that corresponds to exposure opening 110. In the photolithographic technique of the prior art, a contact hole is formed in interlayer dielectric film 106 of semiconductor integrated circuit 100 through this opening 116 in resist 115.
However, since it is impossible to form contact hole 107 of a diameter that is still smaller than the dimension limited by exposure resolution, resist 115 that has been patterned as described hereinabove is heated and softened in a thermal flow process to shrink opening 116 as shown in FIG. 2B.
Since opening 116 of resist 115 thus attains a diameter that is smaller than the exposure limit dimension, an extremely small diameter contact hole 107 can be formed from the surface of interlayer dielectric film 106 to the surface of gate oxide film 102 by etching interlayer dielectric film 106 of semiconductor integrated circuit 100 through opening 116 in resist 115.
Exposure opening 110 of photomask 111, which is used in the exposure process in the above-described thermal flow process, is therefore formed at dimensions that approach the limit dimensions of the exposure process and in a shape that is an enlargement in all directions of opening 116 that has been shrunk by heating resist 115.
When the dimensions of exposure opening 110 approach the exposure limit dimensions, the shape of an exposure beam that passes through exposure opening 110 is deformed by such factors as diffraction. The shape of the exposure of opening 116 in resist 115 is therefore roughly oval in shape even though exposure opening 110 is square, and the shape of opening 116 following the thermal flow process becomes approximately circular.
Since no problem is raised if the plan shape of contact hole 107 that is formed at the exposure limit dimensions as described above is substantially circular, exposure opening 110 of photomask 111 is typically formed as a square in order to simplify design and fabrication. As a result, in a case in which the exposure dimension of opening 116 in resist 115 is set to a circle of diameter “a”, exposure opening 110 of photomask 111 is formed as a square having sides of length “a”.
In the interest of simplifying the explanation here, a case is described in which the process of exposing resist 115 using photomask 111 is carried out in equal proportions, but in a case in which the exposure process is performed in the above-described exposure limit dimensions, the pattern of openings of photomask 111 is typically exposed on resist 115 in a form that is reduced by reduction optics.
After forming opening 116 in resist 115 by an exposure process using photomask 111 in the above-described thermal flow process, this resist 115 is heated to shrink opening 116, whereby a process can be performed on interlayer dielectric film 106 at dimensions that are smaller than the exposure limit dimension.
Nevertheless, when resist 115 is heated and softened to shrink opening 116 that was formed by the exposure process as described hereinabove, opening 116 deforms as it shrinks due to the surface tension of this resist 115. It has been confirmed by the inventors of this invention that this deformation occurs in accordance with the positional relationships between the plurality of openings 116. Specifically, when shrinking a plurality of openings 116 by heating resist 115, the degree of shrinkage at each of openings 116 that are close to each other is smaller in the direction between openings 116 while the degree of shrinking is greater in the direction orthogonal to this direction.
In some types of high-integration DRAM referred to as “¼ pitch DRAM,” for example, a plurality of contact holes 107 are arranged linearly in a direction that is inclined 45° from the directions of arrangement of the bit lines and word lines. Photomask 111 for forming such a plurality of contact holes 107 has a shape in which a plurality of square exposure openings 110 are arranged in a line in a 45° direction, as shown in FIG. 3A.
When resist 115 is exposed using this type of photomask 111, a plurality of round openings 116 is thus arranged in a line in a 45° direction, as shown in FIG. 3B. When this resist 115 is heated and openings 116 are caused to shrink, however, the degree of shrinkage in the direction of arrangement is small, while the degree of shrinkage in the direction orthogonal to this direction is great, and, as shown in FIG. 3C, each of openings 116 therefore forms an oval that is elongated in the direction of arrangement of openings 116.
In a thermal flow process of the prior art, the formation of openings 116 of a desired shape in desired positions is problematic due to deformation according to the positional relationship between the plurality of openings 116, as described in the foregoing explanation, and the proper realization of prescribed fine processing on semiconductor integrated circuit 100 is therefore also problematic.